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VSJ001 / Automated-FPGA-Middleware-for-Power-System-Simulation

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Automated Simulink-to-FPGA pipeline in Python: generates HLS-ready C from a discrete-time power system model (Emergency Diesel Generator), runs Vitis HLS synthesis on Zynq-7000 (xc7z020clg400-1) for 5 step sizes (5-100 us), and compares hardware execution to Simulink reference. 5.5x-6x speedup, 1e-11 to 1e-12 error.

python automation fpga zynq hls rtl xilinx simulink vivado power-systems high-level-synthesis mathworks embedded-coder hardware-simulation vitis-hls
  • Updated May 8, 2026
  • Python

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