This repository contains the synopsis, literature review, methodology, references, and related research material for the research paper titled “AI-Based Routing Algorithm for Network-on-Chip (NoC)”.
The research focuses on improving routing efficiency in Network-on-Chip architectures using Artificial Intelligence techniques such as Reinforcement Learning and Machine Learning-based adaptive routing.
With the increasing demand for multi-core processors and System-on-Chip (SoC) architectures, efficient communication between processing cores has become a major challenge. Traditional deterministic routing algorithms suffer from congestion, latency, and poor adaptability under dynamic traffic conditions.
This research explores AI-driven routing mechanisms capable of dynamically selecting optimal communication paths based on real-time network conditions.
- To study existing routing algorithms in NoC systems
- To analyze limitations of traditional routing methods
- To explore AI-based adaptive routing techniques
- To reduce network congestion and latency
- To improve throughput and communication efficiency
- To compare AI-based routing with conventional routing approaches
The research methodology includes:
- Literature Review
- Data Collection and Analysis
- Traffic Pattern Evaluation
- Reinforcement Learning-based Routing Model
- Simulation and Testing
- Performance Evaluation
Performance metrics considered:
- Latency
- Throughput
- Congestion Rate
- Energy Efficiency
- Scalability
- Python
- TensorFlow / PyTorch
- NoC Simulator
- Artificial Intelligence Concepts
- Reinforcement Learning
The proposed research can be applied in:
- Multi-core processors
- Embedded systems
- High-Performance Computing (HPC)
- AI accelerators
- System-on-Chip (SoC) architectures
- Synopsis PDF
- Literature Review
- Research References
- Methodology
- Simulation Details
- Future Scope
The proposed AI-based routing system is expected to:
- Reduce congestion
- Minimize latency
- Improve throughput
- Provide adaptive routing decisions
- Enhance communication efficiency in NoC systems
Future research may include:
- FPGA/ASIC hardware implementation
- Deep Reinforcement Learning integration
- Power optimization techniques
- Large-scale NoC deployment analysis
The references used in this research are included in the synopsis document and related research materials uploaded in this repository.
Kaustubh Joshi
B.Tech Computer Science and Engineering IILM University, Greater Noida
Under the guidance of Dr. Akash Punhani